View ATA5278_1147758.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* * * * * * * * * * * * * *
SPI for Microcontroller Connection with Up to 1 Mbit/s Internal Data Buffer for Timing-independent Data Transmission Programmable Driver Current Regulation One-chip Antenna Driver Stage for 1 A Peak Current LF Baud Rates Between 1 kbaud and 4 kbaud Quick Start Control (QSC) for Fast Oscillation Build-up and Decay Timing Integrated Oscillator for Ceramic Resonators Power Supply Range from 7.5 V to 16 V Direct Battery Input (Up to 28 V With Limited Function Range) Amplitude Shift Keying (ASK) Modulation Phase Shift Keying (PSK) Modulation Carrier Frequency Range from 100 kHz to 150 kHz Operational Temperature -40C to +105C EMI and ESD According to Automotive Requirements Highly Integrated -- Less External Components Required
Stand-alone Antenna Driver ATA5278
Applications
* * * *
Hands-free Car Access (Passive Entry/Go) Tire Pressure Measurement Home Access Control Care Watch Systems
Preliminary
Benefits
* Diagnosis Function and Overtemperature Protection * Load Dump Protection Up to 45 V for 12 V Boards * Power-down Mode for Minimum Power Consumption
Electrostatic sensitive device. Observe precautions for handling.
Description
The ATA5278 device is an integrated BCDMOS antenna driver IC dedicated as a transmitter for Passive Entry/Go (PEG) car applications and for other hands-free access control applications. It includes the full functionality of generating a magnetic LF field in conjunction with an antenna coil to transmit data to a receiver in a key fob, card or transponder. A microcontroller can access the chip via a bi-directional serial interface.
Rev. 4832A-RKE-10/04
Figure 1. Block Diagram
VL1 VL2 VL3 CINT VBATT VDD OSCI OSCO VIF MODACTIVE NRES CLKO
PGND1 PGND2 PGND3 VDS CBOOST
Boost converter control
5-V regulator
Oscillator Voltage interface
S_CS S_CLK S_DI S_DO
ATA5278
HS driver Control and status register
DRV1 LS driver Driver control logic
SPI
QSC Current and zero crossing sensing LF data buffer
VSHUNT
AGND
DGND
SCANE
TEST
Pin Configuration
Figure 2. Pinning QFN28
VL3 VL2 VL1 VBATT VDD S_DO S_DI PGND1 PGND2 PGND3 VDS DRV1 CBOOST QSC 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 ATA5278 18 17 16 15 8 9 10 11 12 13 14 VSHUNT AGND DGND CINT MODACTIVE NRES SCANE S_CLK S_CS OSCI OSCO VIF CLKO TEST
2
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol PGND1 PGND2 PGND3 VDS DRV1 CBOOST QSC VSHUNT AGND DGND CINT MODACTIVE NRES SCANE TEST CLKO VIF OSCO OSCI S_CS S_CLK S_DI S_DO VDD VBATT VL1 VL2 VL3 Function Boost transistor ground Boost transistor ground Boost transistor ground Driver voltage supply input Antenna driver stage output External bootstrap capacitor connection QSC transistor-gate driver-stage output Antenna current-shunt resistor connection Analog ground (sensoric/antenna driver) Digital ground (logic) External integrator-capacitor connection Modulator status pin output Reset input (inverted) For factory test purposes only (connect to ground) For factory test purposes only (connect to ground) Clock signal output Logic interface voltage supply Oscillator output (for resonator/crystal connection) Oscillator input (for external clock source or resonator/crystal connection) Chip select for serial interface Clock input for serial interface Data input for serial interface Data output of serial interface Internal 5 V stabilizing capacitor connection Battery supply Coil connection for the boost converter low-side switch Coil connection for the boost converter low-side switch Coil connection for the boost converter low-side switch
3
4832A-RKE-10/04
Functional Description
General Description
The IC contains a half-bridge coil driver stage with a special driver voltage regulator and control logic with diagnosis circuitry. It is controllable by a serial programming interface (SPI). In combination with an LC antenna circuitry, the IC generates an electromagnetic LF field. The carrier frequency for the antenna is generated by the oscillator and a prescaler logic. The LF field can be modulated to transmit data to a suitable receiver. Two modulation modes are available: Amplitude Shift Keying (ASK) and 180 Phase Shift Keying (PSK). The transmission data has to be stored in the internal data buffer. The IC consists of two main functional blocks: * * The SPI with the data buffer, the control registers and the oscillator The driver stage with its control logic and the power supply stage
A boost converter is used to supply the driver half-bridge with a high voltage and a regulated current even if the battery voltage is low. The antenna current is programmable in 16 steps to support a transmission with various field strengths. The driver circuitry is protected against short-circuits and overload.
Operational States
After power-on-reset, the ATA5278 is in power-down mode. To achieve minimum power consumption, only the internal 5-V supply and the control registers are active. The IC can only be activated by the external control unit via the serial interface (i.e., the chip select line is enabled). Once activated, the chip keeps the oscillator active and waits for commands on the serial bus. This state can be described as standby mode. Only upon an external reset or on command followed by disabling the chip select line, the power-down mode is reinvoked. The modulator stage, together with the antenna driver and the power supply, is activated as soon as LF data is written into the buffer and remains in this state until all data has been sent, a stop command has been given via the SPI or a fault occurred. The data modulation is running independently of the SPI activity and can be monitored with the MODACTIVE pin.
Power-down Mode
The ATA5278 should be kept in power-down mode as long as the LF channel is not used, because not only is the current consumption minimal, but the internal logic is also reset. The antenna driver stage is in high impedance mode. To power-up the chip, the chip-select line (S_CS) has to be activated for an appropriate time. The SPI then starts the internal oscillator which is necessary for proper operation. Only after a certain oscillation build-up time, is full functionality available. The microcontroller can check out the state of the IC with two state bits automatically returned by any SPI command.
4
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Figure 3. Power-up Timing
S_CS
OSCI/OSCO
Oscillation build-up
Steady oscillation
QSC
DRV1
Z
tstartup Legend: Z = high impedance
tdeb
The startup time, tstartup, in Figure 3 depends on the clock source used in the application. Typical oscillation build-up times are below 100 s for ceramic and about 1 ms for crystal resonators. When using an active clock source, the startup time can be neglected. The internal logic debounces the first clock signals until it finally powers-up the IC for the time tdeb. Note that during this time, the chip select signal S_CS has to be permanently active. The normal way to bring the chip back into power-down mode is to use an SPI command. Deactivating the chip-select line right after the power-down command, an internal standby timer is started and will run for ttimeout = (2048/fOSCI). In this time, the antenna driver stage is stopped to discharge any energies possibly remaining in the antenna circuit. If the chip-select line is reactivated during this time, the sequence is interrupted and the IC remains in standby mode. Otherwise, the power-down mode is engaged after the timeout, the oscillator is stopped and the driver stages are switched to high impedance. Figure 4 illustrates this behavior. Figure 4. Power-down Timing
S_CS
S_CLK
8 CLK
S_DI
cmd 4
DRV1
X
Z
OSC
f = 8 MHz
ttimeout Legend: X = do not care Z = high impedance
Note that if command 4 is omitted and only the chip-select line is disabled, the ATA5278 stays operational (i.e., the oscillator keeps running, an eventually running LF data modulation is not interrupted). Here, only the SPI itself is disabled and the serial bus can be used for other devices connected to it.
5
4832A-RKE-10/04
In case the microcontroller is not able to communicate properly with the ATA5278 or any other disturbance has occurred, it can trigger a reset (like a power-on-reset, POR) in the chip by pulling the NRES pin to ground, which will bring the logic back to the startup state, i.e., all configurations are at default and the IC is in power-down mode. Figure 5. External Reset
OSC
f = 8 MHz
S_CS
X
Int. state
X
POR
Power-down
NRES
tNRES
Oscillator
The ATA5278 is equipped with an internal oscillator circuitry that provides the system clock signal needed for operation. It is intended to work with an externally applied passive reference device such as a ceramic resonator or a crystal. Active clock sources like microcontrollers or crystal oscillators, however, can also be used. Figure 6 shows the internal structure of the oscillator circuitry. Figure 6. Internal Oscillator Circuitry
Enable signal from SPI S1
Pull-down Clock signal judging To internal logic Cin = 12 pF typ. Rfb = 250 k typ. Rd = 420 Cout = 12 pF typ.
OSCI
OSCO
6
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
The main element of this circuit is the parallel inverting stage which generates the clock signal in conjunction with the external reference device. During power-down mode, these inverters are shut down and the pull-down structure on the OSCI pin is active. As soon as the SPI enables the oscillator, the pull-down is disabled and the inverters are powered up. Now, the clock signal assessment stage monitors the signal on the OSCI pin. As soon as the amplitude and the period reach acceptable values, one of the two inverters (i.e., the drivers) is shut down in order to reduce power dissipation in the external reference device. Figure 7 on page 7 illustrates the period assessment. Figure 7. Oscillator Signal Assessment
Oscillator enable signal OSCO signal Second inverter enable signal Clock signal for internal logic
Clock signal for internal logic
t > tLOW,max
t < tLOW,max
I/O Voltage Interface
All digital I/O pins, including the reset input pin NRES, are passed through the internal voltage interface before they reach their concerning blocks. This interface prevents possible compensation currents, as the control logic of the ATA5278 is supplied by the internal 5 V regulator. It is capable of handling I/O voltages between 3.15 V and 5.5 V, determined by the voltage applied to the VIF pin. The pins NRES and S_CS are additionally equipped with a pull-up and a pull-down structure respectively in order to ensure a defined behavior of the ATA5278 in case of a broken connection. If the NRES line is broken, the pull-up structure keeps the input in passive state and normal operation is possible. A broken S_CS line will cause a permanently disabled SPI and S_DO pin, so communication between the microcontroller and other SPI bus members is still possible. For further details on the voltage interface, please refer to the table "Electrical Characteristics" on page 26.
SPI
The control interface of the ATA5278 consists of an eight-bit synchronous SPI. It has a clock input (S_CLK) which supports frequencies up to 1 MHz, a chip select line (S_CS) which enables the interface, a serial data input (S_DI) and a serial data output (S_DO). The output pin is of a tristate type, which will be set to high-impedance state as soon as the chip-select line is disabled. The interface is in slave mode configuration. This means that an SPI master (e.g. a microcontroller) is required for communication with the ATA5278, as the IC will neither start a communication by itself nor is it able to provide the serial clock signal. Figure 8 on page 8 sketches the internal structure.
7
4832A-RKE-10/04
Figure 8. SPI Structure
Internal data bus
8
S_CLK
MSB
6
5
4
3
2
1
LSB
Output register
S_DI
MSB
6
5
4 Input register
3
2
1
LSB
S_DO
tri
S_CS
8
Control logic/internal data bus
Once enabled by the chip-select line, the data at the S_DI pin is shifted into the input register with every rising edge of the input clock signal. At the pin S_DO, the actual data of the LSB of the output register is available. The output register is shifted on every falling edge of the input clock signal. Two timing schemes for SPI data communication are supported, which are shown in Figure 9.
8
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Figure 9. SPI Timing Diagram
tDO,enable S_CS tDI,setup X
tS_CLK,per tS_CLK,h tS_CLK,l tDO,delay tDI,hold
tDO,disable
S_CLK
X
S_DI
X
LSB
Input bit 1
Input bit 2
MSB
X
S_DO
Z
LSB
Output bit 1
Output bit 2
MSB
X
Z
First Possible Serial Timing, S_CLK Polarity 0, Phase 0
tDO,enable S_CS tDI,setup X
tS_CLK,per tS_CLK,h tS_CLK,l tDI,hold tDO,delay
tDO,disable
S_CLK
X
S_DI
X
LSB
Input bit 1
Input bit 2
MSB
X
S_DO
Z
X
LSB
Output bit 1
out
MSB
Z
Second Possible Serial Timing, S_CLK Polarity 1, Phase 1
9
4832A-RKE-10/04
SPI Commands
The microcontroller can access the following functions of the ATA5278 via the SPI: * * * * * * * * Read from/write to configuration register 1 Read from/write to configuration register 2 Read from the status register Write LF transmission data to the buffer and start the transmission Verify the state of the data buffer Clear the fault memory Stop the modulator Enable the power-down mode
Table 1 lists all functions and their definitions. Table 1. SPI Commands
No. 1 I/O I1 O1 I1 O1 I1 O1 MSB 0 SR 0 SR 0 SR 0 SR 0 SR 0 0 0 SR X 0 0 SR 0 0 0 SR X 0 6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 X 0 5 0 0 0 0 1 0 0 0 0 0 IC3 0 0 0 X IC3 0 0 0 0 0 0 X 0 4 0 0 1 0 0 0 0 0 0 0 IC2 0 0 0 X IC2 0 0 0 0 0 0 X 0 3 0 0 0 0 0 0 0 0 0 0 IC1 0 0 0 X IC1 1 0 0 1 1 0 X 0 2 0 0 0 0 0 0 0 0 1 0 IC0 1 1 0 X IC0 0 0 BR1 0 0 0 X BR1 1 0 RTS 0 RTS 0 RTS 0 RTS 0 RTS 0 0 1 RTS X 0 0 RTS BR0 0 1 RTS X BR0 LSB 0 0 1 0 1 0 1 0 0 0 AP 0 0 0 X AP 0 0 PS 0 0 0 X PS Description Check status of IC SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready Reset fault memory SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready Stop modulator SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready Enable power-down mode SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready Write configuration register 1 SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready IC3..0: antenna coil current selector AP: 0 ASK modulation mode, 1 PSK modulation mode Read configuration register 1 SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready IC3..0: antenna coil current selector AP: 0 ASK modulation mode, 1 PSK modulation mode Write configuration register 2 SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready BR1..0: LF data baud rate selector PS: 0 CLKO prescaler disabled, 1 prescaler enabled Read configuration register 2 SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready BR1..0: LF data baud rate selector PS: 0 CLKO prescaler disabled, 1 prescaler enabled
2
3
4
I1
5
I1 O1 I2 O2 I1 O1 I2 O2 I1 O1 I2 O2 I1 O1 I2 O2
6
7
8
10
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Table 1. SPI Commands (Continued)
No. I/O MSB 6 5 4 3 2 1 LSB Description Read status register SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready IC: illegal command received CH: overcurrent in antenna footpoint detected OL: open load detected SH: overcurrent to VBATT detected at driver output SL: overcurrent to GND detected at driver output OT: overtemperature detected Check free LF data buffer space SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready D6..0: free logical LF data bits in buffer Write LF data to buffer and start modulator SR: 0 system not ready, 1 system ready RTS: 0 modulator not ready, 1 modulator ready D6..0: number of logical LF bits to be written into buffer HB7..0: LF half bits (2 for one logical bit) B7..0: input bit from the previous controller data word
9
I1 O1 I2 O2
0 SR X 0
0 0 X 0
0 0 X IC
0 0 X CH
1 0 X OL
1 0 X SH
1 RTS X SL
0 0 X OT
10
I1 O1 I2 O2 I1 O1 Ix Ox
0 SR X 0 1 SR HB7 B7
0 0 X D6 D6 0 HB6 B6
0 0 X D5 D5 0 HB5 B5
0 0 X D4 D4 0 HB4 B4
0 0 X D3 D3 0 HB3 B3
0 0 X D2 D2 0 HB2 B2
1 RTS X D1 D1 RTS HB1 B1
0 0 X D0 D0 0 HB0 B0
11
Command Description
Table 1 on page 10 summarizes the commands interpreted by the SPI control logic of the ATA5278. Each command consists of one or more data words which the controller has to transfer to the SPI of the ATA5278. An SPI data word is always eight bits in width and has to be transferred starting with the least significant bit (LSB). The following list contains detailed information on every command of the chip. * The main purpose of command 1 is to check the operational status of the chip. Only if the System-Ready bit (SR) and the Ready-To-Send bit (RTS) have been received as 1, the ATA5278 is fully functional. In special cases, only the SR bit will be received as 1. This is when the LF data buffer is full or when the power stages have been shut down due to a fault. This command can be used at any time to check the status of the chip. Command 2 is the first out of three special function commands. It is used to reset the internal fault memory. Once a fault is detected by the internal diagnosis stage, it is stored in the fault memory (i.e., the status register) and the power stages are shut down to protect them from damage. In order to enable the chip again, this command has to be sent to the IC. Command 3 can be used to stop the LF data transmission immediately. Regularly, the modulator stage works as long as new (i.e., unsent) LF data is in the data buffer. When using this command, all data in the buffer will be deleted and the antenna driver stage is switched to idle mode. Command 4 has to be used to shut down the IC. In order to start the power-down sequence properly, no further command must be transmitted to the chip and the chip-select line (S_CS) has to be disabled afterwards.
*
*
*
11
4832A-RKE-10/04
*
Command 5 is used to write configuration data into register 1, which is used for LF data modulation control. All register access commands are of a 16-bit structure (i.e., two data words). The first data word defines the access itself (i.e., read or write, and the register number). The second data word is the configuration data, which is to be sent to the ATA5278. Note that in return for the second data word, the first input data word is sent back to the controller. This can be used to validate the SPI transmission. Register 1 contains the four-bit-wide antenna coil current selector (IC3..IC0) and the modulation type selector bit (NASK_PSK). For further details, please refer to the section "Current Adjustment" on page 19. Command 6 can be used to validate a change in register 1 (i.e., a prior command 5 operation) or to check its actual state after a power-down period. Like all register access commands, it consists of two data words. The return data in the second data word has the same bit sequence as in command 5. Command 7 writes configuration data to register 2, which handles timing relevant setup information. Like all register access commands, it consists of two data words, where the second one is the configuration data itself. Note that in return for the second data word, the first input data word is sent back to the controller. This can be used to validate the SPI transmission. Register 2 contains the two-bit-wide LF data baud-rate selector (BR1..BR0) and the pin CLKO prescaler bit. For further details, please refer to the sections "LF Data Modulation" on page 14 and "Clock Supply". Command 8 can be used to validate a change of register 2 (i.e., a prior command 7 operation) or to check its actual state after a power-down period. Like all register access commands, it consists of two data words. The return data in the second data word has the same bit sequence as in command 7. The status register of the ATA5278 can be read out with command 9. As soon as the internal diagnosis stage detects a fault, it is stored in the status register until a fault reset command is given or a power-on-reset occurs. Note that the power stages of the chip are disabled as long as a power stage fault (i.e., a short-circuit at the driver stage output pin, open load, overcurrent at the current sense pin or over temperature) is present in the status register. Like all register access commands, it consists of two data words, where the return data in the second data word contains the fault bits. For further details, please refer to the section "Fault Diagnosis" on page 20. Command 10 accesses a special register, where the actual amount of free logical bits in the data buffer is stored. This value decreases with each logical bit that is transferred to the buffer, and increases with each logical bit the modulator stage fetches from the buffer in order to transmit it via the LF channel. It can be used to determine the amount of data which can be transferred to the buffer or to determine the actual modulation process. Like all register access commands, it consists of two data words, where the second one contains the six-bit-wide value. Command 11 is used to write LF data to the on-chip data buffer and to start the modulator stage. This command is indicated by the most significant bit (MSB) of the first data word from the controller, which is, in contrast to all other commands, 1. The other seven bits of this word determine the amount of logical LF data to be written to the buffer. This amount of data has then to be transferred from the controller to the ATA5278. As one logical bit consists of two half bits, a maximum of four logical bits can be transferred per one SPI data word. With the data buffer being able to store up to 96 logical bits, command 11 may reach a maximum length of 25 SPI data words (i.e., the first word with the amount of data, followed by up to 24 words with the data itself). Note that the input data from the SPI input register is always read out starting from the least significant bit (LSB), working towards the MSB. So if less than four logical bits are transferred to the buffer, they have to be stored in the lower
*
*
*
*
*
*
12
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
area of the SPI data word (i.e., starting with the LSB). It is important that the number of actually transferred LF data matches the amount given in the first word of this command, because there are no consistency checks. This is even then the case if the data buffer was already full at the beginning of the transmission, or got full during the transmission of LF data, or if the driver stages are disabled due to a present fault. Data which is transferred under such circumstances is not stored and therefore lost. The SPI control logic checks the incoming data for valid commands. If the first data word transmitted by the microcontroller does not match any of the above listed functions, an illegal command fault is detected and written into the fault register. It can be read out with command 9, bit 5 (IC). Note that this fault does not cause a shut down of the power stages.
LF Data Buffer
The ATA5278 features an 192-bit wide data storage intended to buffer LF data between the microcontroller and the modulator stage. It can be filled with data via the SPI and therefore at high speeds (i.e., up to 1 Mbit/s). The modulator stage then accesses this buffer with the selected LF baud rate and controls the connected LF antenna accordingly. Hence the controller can handle other tasks during the comparatively slow LF data transmission. The data buffer is structured as a First-In-First-Out (FIFO) system, as can be seen in Figure 10. Figure 10. Structure Of Internal Data Buffer
MSB 6 Input register 5 4 3 2 1 LSB Bit 0 Bit 2 . . . Data buffer . . . . . . Bit 188 Bit 190 Bit 1 Bit 3 . . . . . . . . . Bit 189 Bit 191 LF modulator stage Data pointer 4-1 MUX Upper
Lower
Upper
Lower
The buffer is structured into two parallel blocks with the same storage capacity. The reason for this is that the LF data is handled as logical (e.g., Manchester coded) bits, where each data is encoded by two so-called half bits. The minimum amount of data which can be written to or read from the buffer is one logical bit, hence two half bits.
13
4832A-RKE-10/04
After activating the IC from power-down mode or any fault, the data pointer in Figure 10 on page 13 is at the lowest point of the buffer (i.e., bit 190/191). Any write operation will store the data to the position the pointer is pointing at, and moves it upwards one position. The data is always read from the lowest point of the buffer by the modulator stage. Any read operation will cause the data in the buffer to drop down one position, including the data pointer. Any further writes are ignored if the data pointer reaches the upper border of the buffer, and the LF modulator stage stops operation after the pointer has reached the lower border.
LF Data Modulation
The LF modulator stage of the ATA5278 is fed with data from the LF data buffer. It is started after a successfully received SPI command 11. Two half bits are loaded at a time and brought sequentially to the driver control logic, starting with the half bit labeled lower in Figure 10 on page 13. It is applied for half the period time selected by the LF baud rate selector. Then the half bit labeled upper is applied for the same time. The driver control stage generates a control signal for the power output stages according to the input and the selected modulation mode. The IC has two modulation modes, ASK and PSK. They are selected by the NASK_PSK bit (i.e., bit 0) in control register 1. In ASK modulation mode (NASK_PSK = 0), the IC switches the carrier on and off depending on the value of the half bit applied by the modulator stage, where 1 activates the carrier and 0 deactivates it. So if the carrier is to be activated for a certain time (i.e., continuous wave), a corresponding amount of half bits have to be set to 1 in the LF data buffer. Figure 11 illustrates this behavior.
Figure 11. LF Data Modulation with ASK
Half bit values Driver control input Driver control signal X 0 1 1 0 1 1 1 1 X
Resulting antenna signal
MODACTIVE pin
tBitlength/2 tBitlength
Start of modulation
End of modulation
The LF data stream in Figure 11 has a length of four logical bits and therefore eight half bits. To get this result, a hex value of 0F6h has to be written into the data buffer via the SPI. The time value t Bitrate is the period of one logical bit, which is defined by the selected data baud rate in configuration register 2. Note that the MODACTIVE pin is active even if the half bit at the modulator stage is '0'. In PSK mode (NASK_PSK = 1), the phase of the carrier signal is shifted by 180 on any change of the LF data in the buffer. Taking the same data sequence as in the previous example, the diagram changes shown in Figure 12 on page 15.
14
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Figure 12. LF Data Modulation with PSK
Half bit values Driver control input Driver control signal X 0 1 1 0 1 1 1 1 X
Resulting antenna signal
MODACTIVE pin
tBitlength/2 tBitlength
Start of modulation
End of modulation
The carrier signal is now always on as long as the LF data is in the buffer. It is only at the change of the LF data values that the phase of the antenna current is shifted by 180. For further details, please refer to the section "Driver Stage" on page 16. An internal timer, derived from the system clock generates the modulation times for the half bits applied to the driver stage. These times depend on the selected LF baud rate in configuration register 2 (i.e., the bits BR0 and BR1). Table 2 lists the bit settings and their corresponding timings. Table 2. LF Baud Rate Time Values
BR0 Bit Setting 0 1 0 1 BR1 Bit Setting 0 0 1 1 Selected Baud Rate 1 kbaud 2 kbaud 3 kbaud 4 kbaud Time for One Half Bit tBitlength/2 512 s 256 s 160 s 128 s Time for One Logical Bit tBitlength 1024 s 512 s 320 s 256 s
Note that due to synchronization issues, the time for which the LF field is really active in ASK mode when transmitting one half bit might vary by 8 s. This is a non-accumulating effect, which means, the transmission time for the complete LF data stream may also vary by 8 s, independent of the total amount of logical bits. The same is true for the distance of two phase shifts when transmitting LF data in PSK mode. If data rates above 2 kbauds are demanded or the PSK modulation mode is selected, the use of an external antenna current loop switch is mandatory. This switch has to be controlled in a defined way which is supported by the ATA5278. For further details on this topic, please refer to the section "QSC Feature" on page 16.
15
4832A-RKE-10/04
QSC Feature
The Quick Start Control (QSC) feature supports a short oscillation build up and decay time during LF data modulation. An external high-voltage MOS transistor is used as a switch to close and open the current loop of the antenna. By synchronizing this switch to the zero-crossing events of the antenna current, very short build-up and decay times for the LF field, and therefore high data rates can be achieved. Figure 13. QSC Operation
Half-bit from data buffer Voltage at QSC pin
Current through antenna Modulation in ASK mode Modulation in PSK mode
The gate of the external transistor is driven by the QSC pin of the ATA5278. The signal provided here is suited to drive standard MOSFETs (i.e., no logic-level FETs). During power-down mode or a fault shutdown, the external transistor is switched off. Otherwise, this would lead to a conducting state as long as no data modulation takes place. For further information on this pin, please refer to the table "Electrical Characteristics" on page 26.
Driver Stage
The driver stage of the ATA5278 consists of following blocks: * * * DMOS half-bridge antenna driver Switched Mode Power Supply (SMPS) in boost configuration Antenna current sensor for peak value and zero-crossing detection
All these blocks are controlled by the internal driver control logic. The antenna driver stage itself is supplied by the boost converter output voltage, which is applied at the VDS pin. It consists of two power NMOS transistors in half-bridge configuration. As the high-side transistor requires a control voltage above the output voltage (i.e., a voltage above the supply voltage VDS), a bootstrap configuration is implemented. This circuitry requires an external capacitor of 10 nF to 22 nF, connected between the driver output and the CBOOST pin. This capacitor is charged during the time when the low-side transistor is active. As soon as the low-side transistor is switched off and the high-side transistor starts conducting, both the voltage at the DRV1 pin and the CBOOST pin rises, but always with CBOOST being higher than DRV1 and hence being able to provide an appropriate control voltage for the transistor. Figure 14 on page 17 illustrates this boot strapping configuration.
16
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Figure 14. Bootstrap Configuration Circuitry
CBOOST
Charge supply voltage
VDS
HS transistor
DRV1
LS transistor
High side driver control signal
Low side driver control signal
AGND
The output signal of the antenna driver stage is of a square wave shape. The duty cycle of this signal is dependant on the selected antenna current. For further details, please refer to the section "Current Adjustment" on page 19. The antenna driver stage and the boost converter are thermally monitored in order to protect them from overheating, and the output pin DRV1 is short-circuit protected by means of current limitation. For further details, please refer to the section "Fault Diagnosis" on page 20. The current sensor system is equipped with a zero-crossing detector and a sample and hold stage. The zero-crossing detector provides the synchronization signal for the driver control logic, which then calculates the phase shift between the antenna driver output signal and the current flowing through the antenna. Based on this phase information, the sample and hold stage is controlled in order to sample the top point of the input signal, hence the peak current value.
Current Regulation
A main feature of the ATA5278 is its ability to generate a stabilized magnetic field with a connected LC antenna, mainly independent of the battery voltage and the frequency mismatch between the driver output frequency and the antenna resonance frequency.
17
4832A-RKE-10/04
Figure 15. Antenna Current Regulation Loop
CINT VBAT T
Selected current
+ Integrator
Boost converter
VDS
DRV1
VSHUN T
DMOS half bridge
LC-antenna
Current sample and hold
The input signal for the regulation loop in Figure 15 is the selected antenna current, which is defined in configuration register 1. An external shunt resistor of 1 , which has to be connected to the VSHUNT pin, is used to measure the current in the LC antenna. As the peak voltage over this resistor is directly linked with the peak current in the antenna and hence the magnetic field strength, this value can be seen as output. This signal is sampled and held by an internal stage controlled by the control logic. The difference of the input signal and the sampled signal then controls an integrator. The parameter of this stage can be influenced with an externally applied charging capacitor connected to the CINT pin. The charging/discharging behavior of the integrator stage is described in Figure 16. Figure 16. Integrator Output Current on CINT Pin
30,0
Current at CINT pin (A)
20,0
10,0
0,0
-10,0
-20,0
-30,0 0,5 0,6 0,7 0,8 0,9 1,0 1,1 1,2 1,3 1,4
Voltage at VSHUNT pin (V)
As can be seen in Figure 17, a current is charged into, respectively discharged from the external capacitor depending on the voltage at the VSHUNT pin. Note that the shown values for VSHUNT are only valid if maximum antenna current (i.e., 1 Apeak when using a shunt resistor of 1 ) is selected. When the input voltage reaches the desired value (e.g., 1 V), no current is flowing through the CINT pin and the voltage over the capacitor is not changing. This voltage influences the output voltage of the boost converter. Note that the lower the voltage on the integration capacitor, the higher the output voltage of the boost converter will be. The maximum output voltage is 40 V.
18
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Boost Converter
The ATA5278 provides the supply current for its driver stage by means of a Switch Mode Power Supply (SMPS) in boost configuration. A low-side switch that charges the inductor, and the therefore needed control circuitry is integrated. The other necessary components such as the inductor, the free-wheeling diode and the charging capacitor have to be applied externally. For further details, please refer to the section "Application Hints" on page 22. The SMPS control circuitry is in current-mode configuration. This means that the current through the coil charging transistor (i.e., the current through the VL1..3 and the PGND1..3 pins) is measured and compared to a reference current in each switching period. Should the measured value exceed the reference value, the transistor is switched off and the inductor then discharges its energy through the free-wheeling diode to the charging capacitor. The reference current is generated from the voltage on the CINT pin, hence the integrator output voltage.
Current Adjustment
The maximum reachable output current in the antenna circuit can be calculated as follows: V DRV x 2 I ant,eff = ---------------------------- A x Z Here, VDRV is the maximum reachable driver voltage and Z the antenna's impedance (including the RDSon of the QSC MOSFET, the shunt resistor and the driver output resistance). Note when calculating the amount of complex Z, that the antenna driver output frequency (i.e., f = fOSC/64) has to be taken into account for the complex parts of the impedance. The antenna coil current can be adjusted in 16 steps by modifying the IC0..IC3 bits in the configuration register 1. Dependent on the selected current, the duty cycle of the antenna coil driver signal is adapted. This improves the possibility to use one and the same antenna over the whole range of selectable output currents. Table 3 provides a list of the current settings for all 16 steps. Table 3. Current Settings
Step 1 2 3 4 5 6 7 8 9 10 11 12 13 Note: Current [mA] Imaximum/3.597 Imaximum/3.226 Imaximum/2.976 Imaximum/2.604 Imaximum/2.353 Imaximum/2.132 Imaximum/1.984 Imaximum/1.825 Imaximum/1.709 Imaximum/1.57 Imaximum/1.456 Imaximum/1.361 Imaximum/1.256 1. Default IC0 0 1 0 1 0 1 0 1 0 1 0 1 0 IC1 0 0 1 1 0 0 1 1 0 0 1 1 0 IC2 0 0 0 0 1 1 1 1 0 0 0 0 1 IC3 0 0 0 0 0 0 0 0 1 1 1 1 1 P/P ratio 1.25/6.75 1.25/6.75 1.25/6.75 1.25/6.75 1.75/6.25 1.750/6.25 1.75/6.25 1.75/6.25 2.5/5.5 2.5/5.5 2.5/5.5 2.5/5.5 4/4
19
4832A-RKE-10/04
Table 3. Current Settings (Continued)
Step 14 15 16 Note:
(1)
Current [mA] Imaximum/1.163 Imaximum/1.081 Imaximum 1. Default
IC0 1 0 1
IC1 0 1 1
IC2 1 1 1
IC3 1 1 1
P/P ratio 4/4 4/4 4/4
Fault Diagnosis
The IC contains several fault diagnosis systems to protect itself from destruction and to provide diagnosis information. If a fault at the power stages is detected for a certain debounce time, both the switch mode power supply and the antenna driver stage including the external NMOS transistor (if present) are switched off and the corresponding fault information is written into the status register. Also the LF data buffer is cleared. The fault information can be read out with SPI command 9. In order to restart the operation of the power stages, the status register has to be cleared by transmitting SPI command 2. The following protection and diagnosis mechanisms are defined: * A temperature monitoring system detects critical junction temperatures. Once detected, the debounce timer is started. If the temperature is still above the critical limit after the debouncing time has passed, a fault shutdown is performed. A short-circuit protection of the antenna driver output is realized by means of internal shunt-voltage monitoring. Both the high-side and the low-side transistors are equipped with a shunt resistor which provides information about the current flowing through them. If the current through one of the transistors surpasses the internally defined overcurrent level, a current limitation is invoked immediately and the debounce timer is started. Should this condition persist for the whole debouncing time, a fault shutdown is performed. The current through the external high-voltage MOSFET is monitored in order to detect short-circuits on the return line of the antenna. Like for the other faults, a debounce timer is started as soon as an overcurrent situation is detected and a fault shutdown is performed after this time has passed. The signal at the VSHUNT pin is monitored while the driver stage is active in order to detect a broken antenna connection (i.e., an open load failure). The monitor searches for polarity changes in the signal and starts the fault debouncing timer if it fails to find such changes. A fault shutdown is performed if this fault persists for the whole debouncing time. The input register of the SPI is scanned for illegal commands. Note that this kind of fault will cause neither a shutdown of the power stages nor a clearing of the LF data buffer. This diagnosis function is just to provide information about problems on the SPI bus. Also, no debouncing time is applied for this fault.
*
*
*
*
Some faults, like open load or a short-circuit of the antenna output pin to ground, can only be detected while the driver stage is active (i.e., in modulation mode). As the lowside antenna driver transistor and the QSC transistor are also both active in standby mode, faults concerning these devices are also monitored then. Only during powerdown, no fault monitoring is active. Figure 17 on page 21 illustrates the fault shutdown timing sequence.
20
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Figure 17. Fault Shutdown Timing
t < tdeb,min t > tdeb,min Fault is latched in status register afterwards
Internal fault signal Driver output stage Boost converter operation QSC gate signal MODACTIVE pin X
1
X
Z
1
0
1
0
1
0
Note: Internal fault signal rises as soon as a fault (overtemperature, short-circuit or open load) is detected
Figure 17 shows the sequence of a fault shutdown during the antenna driver-stage being active. If a critical condition persists for a time shorter than the debouncing time (e.g., caused by interferences), no shutdown will occur. The diagnosis bits are based in the status register and are encoded as shown in Table 4. Table 4. Diagnosis Bits (Status Register)
Bit Position 0 (LSB) 1 2 3 4 5 6 7 (MSB) Bit Name OT SL SH OL CH IC Fault Type Overtemperature detected Antenna driver output pin has overload to Ground Antenna driver output pin has overload to VDS (VBATT) Open load detected (no oscillation at VSHUNT pin) Overcurrent at antenna return line (QSC drain input) detected Illegal command in the SPI input register found Not defined Not defined
CLKO Output Pin
The clock output pin CLKO of the ATA5278 can be used to supply an on-board microcontroller with a clock signal (either 4 MHz or 8 MHz). This signal is not suited to supply any device beyond the PCB boundaries. The clock signal is directly derived from the clock source connected to the OSCI/OSCO pins of the ATA5278 and is available as long as the ATA5278 is not in power-down mode. The frequency can be selected with the prescaler (PS) bit in configuration register 2, which is 0 for the full-clock rate (fCLKO = f OSCI) or 1 for the half clock-rate (fCLKO = fOSCI/2).
21
4832A-RKE-10/04
MODACTIVE Output Pin
The MODACTIVE pin of the ATA5278 can be used to directly control a timer/counter stage of the microcontroller. The signal indicates LF data modulation activity. In conjunction with suited timers and counting stages in the microcontroller, it enables the software to precisely know the progress of the LF data transmission. For further details, see Figure 11 on page 14 and Figure 12 on page 15 in the section "LF Data Modulation" on page 14. The ATA5278 is equipped with an internal supply unit that provides supply and reference voltages and currents. This unit is directly supplied by the VBATT pin. During power-down mode, only the 5 V voltage regulator is active. This regulator requires an external capacitor applied to the VDD pin because during operations high peak currents may occur which must be buffered by the external device. For further details on this issue, please refer to the section "Application Hints" on page 22. The Power-On-Reset (POR) is also generated in the internal supply section. The VDD voltage level is monitored permanently and compared with the regular output level. As soon as the actual level is lower than the POR threshold, VPOR, a reset is triggered and held for at least 30 s.
Internal Supply Unit
Application Hints
The following Figure 18 sketches an application using the ATA5278.
Figure 18. Typical Application Circuit With ATA5278
VBATT (min. 7 V) D1 C1 Microcontroller supply L1 VDD X1 N_RES P_IN1 P_IN2
C2 VL1 VL2 VL3
C3
MODACTIVE
CINT
VBATT
VDD
OSCI OSCO VIF NRES
CLKO
D2
C
PGND1 PGND2 PGND3 VDS C4 C5 Ant
LA
Boost converter control
S_CS 5-V regulator Oscillator Voltage interface S_CLK S_DI S_DO
S_CS S_CLK S_DI S_DO
ATA5278
HS driver Control and status register
CBOOST
DRV1 LS driver QSC Current and zero crossing sensing Driver control logic
SPI
LF receiver
VSHUNT Data T1 HVNMOS
LF data buffer
RShunt
AGND
DGND
TEST
GND
SCANE
The external components used in this schematic are listed in Table 5.
22
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Table 5. List of Used Components
Element D1 D2 L1 C1 C2 C3 C4 C5 R1 XTAL T1 Description Standard diode Fast Shottky diode, VBR 50 V, ID 2.5 A Choke, ISAT 4 A, RESR 50 m, L = 22 H Storage capacitor, C 220 F, V 50 VDC Ceramic (chip) capacitor, 33 nF C 100 nF Ceramic (chip) capacitor, C 150 nF Low ESR capacitor, 4,7 F C 22 F, V 50 VDC, RESR 0.8 Ceramic (chip) capacitor, C = 10 nF, V 50 VDC Shunt resistor, R = 1 (1%), Pmax 0.6 W Crystal or ceramic resonator, fRES = 8 MHz High voltage N-channel MOSFET, VDS,max 600 VDC, CGS 2.5 nF
The following basic hints should be considered when designing an application with the ATA5278. * Principally, the values for the external choke and the storage capacitor used in the switched-mode power supply are not fixed, several performance factors, however, are directly linked to these values. The parameters given in Table 5 on page 23 are already optimized to the needs of the internal circuitry and the application. The clock supply for the ATA5278 can be either an active clock source connected to the OSCI pin, or a passive device like a crystal or a ceramic resonator. When using a crystal, the prolonged oscillation build-up time (typically up to 1 ms) needs to be considered. Full functionality of the chip will only be available after the oscillation has reached a stable state. The external HV-MOSFET for the QSC feature should have a low RDSon value, as this value contributes to the quality factor of the LC antenna circuitry. Furthermore, only standard gate input types may be used. TTL-compatible gate inputs might get destroyed by the driving voltage of the QSC pin. The VIF pin must be connected to the supply voltage with which the microcontroller and possible other SPI bus members are driving the SPI bus. The VDD pin is intended to be connected to a stabilizing capacitor only. It is not suited for driving any loads. The bootstrap capacitor C5 should not exceed values of 22 nF, as the internal charging and clamping circuitry can handle only limited currents. The value of the integrator capacitor C2 influences the current regulation speed. The higher the capacitor, the slower the supply voltage for the antenna driver stage and thus the current in the antenna is changed. For more details, please refer to the section "Current Regulation" on page 17. The power dissipation of the ATA5278 mainly depends on the supply voltage and the selected antenna current. It is strongly recommended to solder the exposed die pad to the PCB and to provide vias from the top layer (chip soldering side) to the bottom layer, on which a copper plate, as big in size as possible, can dissipate the heat. This plate can be connected to ground. The ground pin of RSHUNT, C2, C4 and the AGND pin should be connected together as closely as possible. The same is true for the connection between L1, D2 and VL1..3 and the connection between D2, the positive pin of C4 and the VDS pin.
*
*
* * * *
*
*
23
4832A-RKE-10/04
Note that in any case, the test pins SCANE and TEST must be connected to ground. These pins are for factory test purposes only. For safety reasons, these pins are equipped with a pull-down structure, so that the signals are still defined in case of broken connections. Connecting them to any signal other than ground will result in malfunctions which can lead to the destruction of the chip or the external components. The power dissipation of ATA5278 is, as already noted, dependant of the supply voltage and the selected antenna current. Assuming an antenna with maximum allowable impedance (i.e., the boost converter will generate 40 V output voltage) and the maximum available output current selected (i.e., step 16), the power dissipation of ATA5278 results as shown in Figure 19 on page 24 Figure 19. Power Dissipation versus Supply Voltage
8
Power Dissipation [W]
7 6 Ta = 105C 5 4 3 2 1 7.5 Ta = 85C
8.5
9.5
10.5
11.5
12.5
13.5
14.5
15.5
16.5
Voltage at VBATT Pin [V]
The static thermal resistance of the chip, soldered onto a PCB can hardly be lowered beneath 30 K/W. Hence, a static operation of ATA5278 is not possible in all cases. But as most applications require only a temporary LF field, the dynamic thermal effects (i.e., the thermal capacitances) are important parameters that must be taken into account. Figure 20 shows the maximum reachable LF carrier duration for an example PCB design. Figure 20. Operation Cycle Duration versus Power Dissipation
0.6
0.5
Maximum Duration for Single CW [s]
0.4 Ta = 85C 0.3
0.2 Ta = 105C 0.1
0.0 1.5 2.5 3.5 4.5 5.5 6.5 7.5
Power Dissipation [W]
24
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Note that the upper limit of this diagram (0.6 s) is not a design parameter but just for representation reasons. The graphs continue to increase beyond the top line. For this diagram, following parameters have been taken: * The total thermal resistance is 35 K/W, composed of 10 K/W for the junction-to-case resistance Rth,jc, 5 K/W for the case-to-copper resistance Rth,cpcb and 20 K/W for the copper-to-ambient resistance Rth,pcba For the thermal capacitances, the package with an equivalent capacitance of approximately 15 mJ/K and one PCB copper layer with dimensions of 50 mm x 50 mm x 0.05 mm, resulting in 0.426 J/K have been taken The thermal shutdown of the chip triggers at 150C junction temperature
*
*
The thermal resistance Rth,jc and the thermal capacitance of the package are fixed values, but everything behind (i.e., the thermal resistance between the solder pad and ambient and the thermal capacitance of the copper layer(s)) depend only on the PCB design.
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Input voltage (power pins) Input voltage (interface pins) Static power dissipation (Tamb = 85C) Emission Minimum ESD protection (HBM, 100 pF through 1.5 k) Junction temperature Storage temperature range Note: 1. Voltages are given relative to VSS. Symbol VBATT VINP VIND Ptot EMI Value(1) -0.3 to +44 VSS -0.3 VIN 46,5 VSS -0.3 VIN 5.5 2 250 1.5 (pins 7, 17, 26-28 versus other pins) 2 (all other pins versus each other) 2 (all pins versus GND) 4 (pins 5, 6, 7, 8 vs. GND) 150 -55 to +150 Unit V V V W V/M
ESD
kV
TJ Tstg
C C
Thermal Resistance
Parameters Thermal resistance junction-case Thermal resistance junction-ambient (QFN28)(1) Note: Symbol RthJC RthJA Value 10 32 Unit K/W K/W
1. To reach this value, special measures on the PCB have to be taken
Operating Range
Parameters Power supply range Operating temperature range Note:
(1)
Symbol VBATT Tamb
Value 7.5 to 16.5 -40 to +105
Unit V C
1. For details, please refer to the section "Application Hints" on page 22 on maximum allowed operation temperature.
25
4832A-RKE-10/04
Electrical Characteristics
6.5 V < VBATT < 16.5 V, Tamb = 25C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30% decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case. No. 1 1.1 Parameters Power Supply Supply current in powerdown mode Supply current in standby mode Internal 5 V supply Supply cap discharging current Power-down mode driver stage supply current Standby mode driver stage supply current Voltage interface supply current Power-on-reset level I/O Voltage Interface Interface operation voltage Input high level Input low level Input hysteresis Input pull-down current Input pull-up current -40C Tamb +105C -40C Tamb +105C -40C Tamb +105C VIN = 5 V VVIF = 5 V VIN = 0 V VVIF = 5 V VIN = 5 V VIN = 0 V IOUT = -1 mA IOUT = 1 mA VS_CS = 0 V VS_DO = 2.5 V VVIF = 5 V 17 13, 20-22 13, 20-22 13, 20-22 14, 15, 20 13 VVIF VINH VINL VIN,hyst IIN,pd IIN,pu IIN,leak VOUTH VOUTL IODIS tRESHLD -300 135 0,03 x VVIF 15 -16 3.15 0.6 x VVIF 0.3 x VVIF 0,09 x VVIF 60 -4 5.5 V V V V A A D A A A A A VVBATT = 12 V -40C Tamb 105C VVBATT = 12 V VVBATT = 12 V VVBATT = 28 V VVBATT = 40 V VVBATT = 12 V VVDS = 40 V VVBATT = 12 V VVDS = 12 V Pin 7 open VVIF = 5.5 V All outputs open 25 ISUP,0 ISUP,1 VVDD IDISC1 IDISC2 IVDS,0 7 4.7 0.1 3.5 30 40 A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.2 1.3 1.4
25 24 25
9 5.5 1.5 8 0.5
mA V mA mA A
A A A
1.5
4
A
1.6
4
IVDS,1 IVIF VPOR
1.2
2.2
mA
A
1.7 1.8 2 2.1 2.2 2.3 2.4 2.5 2.6
17 24
0.5 VVDD - 0.8 VVDD 0.35
A V
A A
2.7
Input leakage current
21, 22 12, 16, 23 12, 16, 23 23 13, 20
-300 0.8 x VVIF
+300
nA
A
2.8 2.9
Output source capability Output sink capability Output off-state leakage current Reset prolonging time
V 0.2 x VVIF +300 500 V
A A
2.10 2.11
nA ns
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
26
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30% decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case. No. 2.12 3 Parameters Reset hold time Antenna Driver Stage High-side driver on resistance VVDS = 12 V VCBOOST = 18 V IDRV1 = -200 mA Tamb = 105C VVDS = 12 V ILoad = 200 mA Tamb 105C Trans. between 20% and 80% Trans. between 80% and 20% VVDS VVDS = 26 V RLoad = 8.2 VVDS = 26 V RLoad = 8.2 VVDS = 0 V ICBOOST = 5 mA Rising signal on VSHUNT pin Voltage jump on VSHUNT pin from -100 mV to +100 mV RSHUNT = 1 VCINT = 1.9 V VVSHUNT = 750 mV VCINT = 1.9 V VVSHUNT = 1250 mV VCINT = 2.8 V VCINT = 1 V Current step 16, VVSHUNT,p = 1010 mV Current step 1, VVSHUNT,p = 278 mV Test Conditions VNRES 0.3 x VVIF Pin 13 Symbol tNRES Min. 10 Typ. Max. Unit ns Type* D
3.1
4, 5
RDS,HS
1.1
A
3.2
Low-side driver on resistance Switching delay from LS to HS Switching delay from HS to LS HS current limitation LS current limitation Bootstrap capacitor clamping voltage Current Sensing Zero crossing detection threshold Zero crossing detection delay Shunt resistor overcurrent detection level Nominal operation integrator source current Nominal operation integrator sink current Integrator upper voltage limiting current (sink) Integrator lower voltage limiting current (source) Integrator current dependency from antenna current Integrator current for antenna current step 1
5, 9
RDS,LS tdLH tdHL ILIM,HS ILIM,LS VBSOUT, max 75
1.1
ns
A
3.3
5
150
A
3.4
5
220
400
ns
A
3.5 3.6 3.7 4 4.1
5 5 6
1.1 2.0 8
1.8 2.8 11
A A V
A A A
8
VZC
8
55
mV
A
4.2
8
tdZC
300
ns
A
4.3 4.4
8 11
IQSCSC IINTSRC IINTSINK ILIMUP ILIMLOW dICINT
2.3 16
2.7 24
A A
A A
4.5
11
-24
-16
A
A
4.6 4.7
11 11
40 -70
140 -30
A A
A A
4.8
11
350
550
1000
nA
A
4.9
11
ISMPL1
-0.834
+0.834
A
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
27
4832A-RKE-10/04
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30% decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case. No. 4.10 Parameters Integrator current for antenna current step 2 Integrator current for antenna current step 3 Integrator current for antenna current step 4 Integrator current for antenna current step 5 Integrator current for antenna current step 6 Integrator current for antenna current step 7 Integrator current for antenna current step 8 Integrator current for antenna current step 9 Integrator current for antenna current step 10 Integrator current for antenna current step 11 Integrator current for antenna current step 12 Integrator current for antenna current step 13 Integrator current for antenna current step 14 Integrator current for antenna current step 15 Integrator current for antenna current step 16 Test Conditions Current step 2, VVSHUNT,p = 310 mV Current step 3, VVSHUNT,p = 336 mV Current step 4, VVSHUNT,p = 384 mV Current step 5, VVSHUNT,p = 425 mV Current step 6, VVSHUNT,p = 469 mV Current step 7, VVSHUNT,p = 504 mV Current step 8, VVSHUNT,p = 548 mV Current step 9, VVSHUNT,p = 585 mV Current step 10, VVSHUNT,p = 637 mV Current step 11, VVSHUNT,p = 687 mV Current step 12, VVSHUNT,p = 735 mV Current step 13, VVSHUNT,p = 796 mV Current step 14, VVSHUNT,p = 860 mV Current step 15, VVSHUNT,p = 925 mV Current step 16, VVSHUNT,p = 1000 mV Pin 11 Symbol ISMPL2 Min. -0.93 Typ. Max. +0.93 Unit A Type* A
4.11
11
ISMPL3
-1.038
+1.038
A
A
4.12
11
ISMPL4
-1.152
+1.152
A
A
4.13
11
ISMPL5
-1.275
+1.275
A
A
4.14
11
ISMPL6
-1.407
+1.407
A
A
4.15
11
ISMPL7
-1.512
+1.512
A
A
4.16
11
ISMPL8
-1.644
+1.644
A
A
4.17
11
ISMPL9
-1.755
+1.755
A
A
4.18
11
ISMPL10
-1.911
+1.911
A
A
4.19
11
ISMPL11
-2.061
+2.061
A
A
4.20
11
ISMPL12
-2.205
+2.205
A
A
4.21
11
ISMPL13
-2.388
+2.388
A
A
4.22
11
ISMPL14
-2.58
+2.58
A
A
4.23
11
ISMPL15
-2.775
+2.775
A
A
4.24
11
ISMPL16
-3
+3
A
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
28
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30% decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case. No. 4.25 5 5.1 Parameters Antenna current regulation precision Boost Converter Boost switch transistor leakage current Boost switch transistor on resistance Switching frequency Minimum switch-on time per period Maximum switch-on time per period Switching-on signal fall time Switching-off signal rise time Switch-off current threshold Switch-off current slope compensation Overvoltage shut-down level Overtemperature shutdown level (junction temperature) QSC Transistor Driver VVDS = 40 V no DC load on pin QSC, -40C Tamb +105C VVDS = 12 V IQSC = -40 mA -40C Tamb +105C VVDS = 40 V IQSC = 40 mA -40C Tamb +105C VVDS = 8 V CLoad = 2 nF 10% to 90% transition Tamb = 105C fBoost = 250 kHz fBoost = 250 kHz IVL1..3 = 0.4 A IVL1.3 = 0.4 A IVL = 1.25A VCINT = VCINT from meas. 5.8 VVL1-3 = 18 V -40C Tamb +105C IVL1..3 = 1 A Tamb 105C 26-28 26-28, 1-3 26-28 26-28 26-28 26-28 26-28 11 26-28 4 IVL,Leak RDSon fBoost tDCL tDCH tf,Boost tr,Boost VCINT1 dICUT/dt VVDSLIM TOTBoost 41 0 3750 20 20 2.2 0.85 46.5 500 nA A Test Conditions Pin Symbol Min. -6 Typ. Max. +6 Unit % Type* C
5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10
270 fOSCI/32 100 3910 80 80 2.8
m Hz ns ns ns ns V A/s V
A D A A A A A A A
5.11 6
26-28
150
170
C
B
6.1
Maximum output voltage
7
VQ,max
11
16
V
A
6.2
High-side output voltage under load
7
VQ,min
8.5
12
V
A
6.3
Low-side output voltage under load
7
VQ,off
0.2
0.5
V
A
6.4
Switch-on signal rise time
7
tr,QSC
100
200
ns
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
29
4832A-RKE-10/04
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30% decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case. No. Parameters Test Conditions VVDS = 8 V CLoad = 2 nF 90% to 10% transition VVDS = 12 V ICBOOST = -10 mA Pin Symbol Min. Typ. Max. Unit Type*
6.5
Switch-off signal fall time
7
tf,QSC
40
90
ns
A
6.6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8
Bootstrap capacitor charging voltage SPI Clock frequency Clock signal high time Clock signal low time Input signal setup time Input signal hold time Output signal enable time Output signal disable time Output signal delay time Oscillator
6
VBSOUT, min
5.5
10
V
A
21 21 21 22 22 23 23 23 Ceramic resonator, crystal or external clock source -40C Tamb +105C VOSCI = 5 V VOSCO = 4 V VOSCI = 5 V VOSCO = 3 V VOSCI = 0 V VOSCO = 1.45 V VOSCI = 0 V VOSCO = 0.8 V VOSCI < 0.5 x VVDD Power-down mode, VOSCI = 5 V VOSCO = 5 V
fS_CLK tS_CLK,h tS_CLK,l tDI,setup tDI,hold tDO,enable tDO,disable tDO,delay 4/fOSCI 4/fOSCI
fOSCI/8
Hz s s
D D D D D D D D
100 100 100 100 100
ns ns ns ns ns
8.1
Input frequency range
19
fOSCI
8
MHz
D
8.2 8.3 8.4 8.5 8.6
Feedback resistance Startup sink current Operation sink current Startup source current Operation source current Maximum OSCI lowtime for clock driver to stay in operation mode Oscillator input pulldown current Switch-on debounce time after clock signal is stable
18, 19 18 18 18 18
RFB,OSC IL1 IL2 IH1 IH2 tLOW,max
140 2.0 1.2 -3.7 -2.0
400 3.7 1.8 -2.0 -1.2
k mA mA mA mA
A A A A A
8.7
19
660
ns
D
8.8
19
IOSCI,PD
100
250
A
A
8.9
tdeb
192/fOSC
s
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
30
ATA5278 [Preliminary]
4832A-RKE-10/04
ATA5278 [Preliminary]
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30% decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case. No. 9 9.1 Parameters Fault Diagnosis Debounce time for driver stage faults Debounce time for antenna return line faults Debounce time for overtemperature fault DRV1 short-circuit to VBATT or GND QSC input shortcircuit to VBATT open load 5 tdeb,min tdeb,min tdeb,min 120 120 160 20 32 s D Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
9.2
8
s
D
9.3
s
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Soldering Recommendations
Parameters Maximum heating rate Peak temperature in preheat zone Duration of time above melting point of solder Peak reflow temperature Maximum cooling rate Symbol TD ZPH tMP TPeak TrPeak Value 1 to 3 100 to 140 Minimum 10 Maximum 75 220 to 225 2 to 4 Unit C/s C s C C/s
31
4832A-RKE-10/04
Ordering Information
Extended Type Number ATA5278-PKQ Package QFN28 Remarks 7 mm x 7 mm, taped and reeled
Package Information
32
ATA5278 [Preliminary]
4832A-RKE-10/04
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) Atmel Corporation 2004. All rights reserved. Atmel (R), logo and combinations thereof are registered trademarks, and Everywhere You Are SM are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
Printed on recycled paper.
4832A-RKE-10/04

▲Up To Search▲

Price & Availability of ATA5278

	To Download ATA5278 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .